november 2011 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 www.fairchildsemi.com 1 FDMC7696 n-channel powertrench ? mosfet FDMC7696 n-channel powertrench ? mosfet 30 v, 12 a, 11.5 m features ? max r ds(on) = 11.5 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 14.5 m at v gs = 4.5 v, i d = 10 a ? high performance technology for extremely low r ds(on) ? termination is lead-free and rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced power trench ? process that has been especially tailored to minimize the on-state resistance.this device is well suited for power management and load switching applications common in notebook computers and portable battery packs. applications ? dc/dc buck converters ? notebook battery power management ? load switch in notebook g s s s d d d d 5 6 7 8 3 2 1 4 1 2 3 4 5 d d d d g s s s bottom top mlp 3.3x3.3 6 7 8 pin 1 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage (note 4) 20 v i d drain current -continuous (package limited) t c = 25c 20 a -continuous (silicon limited) t c = 25c 38 -continuous t a = 25c (note 1a) 12 -pulsed 50 e as single pulse avalanche energy (note 3) 21 mj p d power dissipation t c = 25c 25 w power dissipation t a = 25c (note 1a) 2.4 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 5.0 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity FDMC7696 FDMC7696 mlp 3.3x3.3 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 FDMC7696 n-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 14 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v1 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v 100na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.2 2.0 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 12 a 8.5 11.5 m v gs = 4.5 v, i d = 10 a 11.5 14.5 v gs = 10 v, i d = 12 a, t j = 125 c 11.6 15.7 g fs forward transconductance v ds = 5 v, i d = 12 a45s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz 1075 1430 pf c oss output capacitance 380 505 pf c rss reverse transfer capacitance 40 55 pf r g gate resistance 0.2 1.0 2.0 t d(on) turn-on delay time v dd = 15 v, i d = 12 a, v gs = 10 v, r gen = 6 918ns t r rise time 210ns t d(off) turn-off delay time 19 33 ns t f fall time 210ns q g total gate charge v gs = 0 v to 10 v v dd = 15 v, i d = 12 a 16 22 nc q g total gate charge v gs = 0 v to 5 v811nc q gs gate to source charge 3.2 nc q gd gate to drain ?miller? charge 1.8 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 1.9 a (note 2) 0.75 1.2 v v gs = 0 v, i s = 12 a (note 2) 0.84 1.2 t rr reverse recovery time i f = 12 a, di/dt = 100 a/ s 25 40 ns q rr reverse recovery charge 9 18 nc notes : 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 21 mj is based on starting t j = 25 c, l = 0.3 mh, i as = 12 a, v dd = 27 v, v gs = 10 v. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. a. 53 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 125 c/w when mounted on a minimum pad of 2 oz copper.
www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 FDMC7696 n-channel powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 0.00.51.01.52.02.5 0 10 20 30 40 50 v gs = 4.0 v v gs = 4.5 v v gs = 3.5 v v gs = 6 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 1020304050 0 1 2 3 4 5 6 v gs = 4.0 v v gs = 6 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 5 10 15 20 25 30 35 40 t j = 125 o c i d = 12 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 12345 0 10 20 30 40 50 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 FDMC7696 n-channel powertrench ? mosfet figure 7. 0 4 8 12 16 0 2 4 6 8 10 i d = 12 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 10 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 30 c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 1 10 40 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 v gs = 4.5 v limited by package r t jc = 5.0 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 1 s 100 p s 10 ms dc 10 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 FDMC7696 n-channel powertrench ? mosfet figure 13. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDMC7696 rev.c8 FDMC7696 n-channel powertrench ? mosfet notes: a. except as noted, package conforms to jedec registration mo-240 variation ba.. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. seating plane is defined by terminal tips only e. body dimensions do not include mold flash protrusions nor gate burrs. f. flange dimensions include interterminal flash or protrusion. interterminal flash or protrusion shall not exceed 0.25mm per side. g. it is recommended to have no traces or via within the keep out area. h. drawing filename: mkt-mlp08trev1. i. general radii for all corners shall be 0.20mm max. b 0.10 cab 0.05 c top view bottom view 0.10 c 0.08 c 0.05 0.00 0.10 c 2x 2x side view seating plane 0.10 c (0.20) 8 5 1.95 0.65 pin1 ident 0.37 0.27 4 1 (8x) 2.32 2.22 0.50 0.40 (4x) (1.20) 0.50 0.40 2.10 2.00 (0.40) 11? ax c 0.8 max a recommended land pattern 3.30? .10 3.30? .10 a keep out area (3.40) 2.37 0.45(4x) (1.70) 2.15 (0.65) 0.42(8x) 0.70(4x) 0.65 1.95 (0.40) a 4 1 85 dimensional outline and pad layout
FDMC7696 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMC7696 rev.c8 trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, us ed under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written appro val of fairchild semiconductor corporation. as used here in: 1. life support dev ices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury of the user. 2. a critical component in any compo nent of a life su pport, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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